HP NMOS-III

13.08.2010 18:43

Last week when I wrote about the Hewlett Packard 9000 I stumbled upon the High-Density Interconnect handbook. I got intrigued by a caption mentioning "stacked transistors" in relation to the HP FOCUS microprocessor that the 9000 series used. I went and dug a little deeper to see if I could find out what was meant by that phrase.

At that time HP was using the NMOS-III fabrication process, which was the successor to the NMOS-II. This was a 1 μm, two-metal layer process designed specifically for their new 32-bit 500.000 transistor FOCUS microprocessor.

I found a pretty detailed description of the technology in the HP Journal. The August 1983 issue is dedicated to the VLSI process while September 1987 deals with higher-level microprocessor architecture. Both are an interesting read for anyone that is into vintage integrated circuit technology.

Illustration of the NMOS-III process (from HP Journal, August 1983)

For instance, unlike CMOS circuits of today NMOS digital circuits had relatively large output impedance and drew a large quiescent current. First property became apparent when chips where unable to drive long PCB traces. This was especially problematic for the system's 18 MHz clock which had to be distributed throughout the computer. So they made a dedicated clock generator chip with gigantic output transistors (55 mm gate width!) and mounted everything on finistrates - special printed circuit boards with wire bonded dies, very small vias and very high-quality Teflon dielectric - all to decrease trace inductance as much as possible. Finistrates also helped solve the heating problem by having a thick copper core which conducted heat away from the components.

Remember the "self healing" RAM they mention in that advert? That was achieved with special polysilicon fuses which allowed the RAM chip to isolate defective parts by melting a part of the interconnect. Oh, and RAM used a four-transistor dynamic cell, unlike one-transistor commonly used today.

Fascinating stuff. Especially considering this was all published in a journal and not kept as a closely kept company secret.

However I didn't find what I was looking for. There is no mention of transistor stacking. On thing is clear though: NMOS-III process certainly did not have any provisions for vertical stacking of transistors (which is rare even today). So that caption most probably referred to some kind of circuit topology.

Posted by Tomaž | Categories: Digital

Add a new comment


(No HTML tags allowed. Separate paragraphs with a blank line.)