## Regulator stability and capacitive load

10.05.2010 21:58

A lab power supply should work reliably under a wide range of loads. Capacitive loads are common - most circuits include at least one blocking capacitor on the power rail and this capacitor often defines the characteristics of the device as seen by the power supply. However capacitive loads are also the most problematic for the final linear regulator stage, because they affect the open-loop transfer function of the feedback.

Here's a simplified schematic diagram of a linear regulator: The differential amplifier block usually includes an op-amp, compensation circuit, driver and power transistors. Only its output resistance is shown here. The feedback comes from a voltage divider R1 R2 which is connected to the negative terminal. To calculate the open-loop transfer function Uout/Uin, the divider has been disconnected from the amplifier. The solid line here shows the amplitude Bode open-loop plot for a typical setup. The op-amp has 100 dB of gain and has been compensated with a dominant pole at 10 Hz resulting in 100 kHz of bandwidth. Divider has 20 dB of attenuation. Say Rout is about 100 mΩ.

What happens when you connect a capacitor to the output terminal of the regulator? Together with Rout it forms a new pole (for instance at fp, shown approximately on the picture for a 4700 μF capacitor).

This creates a stability problem, because the plot passes 0 dB gain at a phase shift greater than 135°. If you look carefully, the loop is stable only if the new pole is created in two regions: at far left (less than 1 mHz) or far right (more than 100 kHz). This translates to capacitances between 1600 F and 16 μF.

The far left region obviously isn't interesting because it would require unrealistically large capacitors. However there is a range of capacitances greater than 16 μF that is occupied by common electrolytic capacitors that will put the feedback loop into instability.

This might appear as a grave problem at first. But it turns out there's nothing like a naked capacitor out there. Electrolytic capacitors actually have quite large effective series resistances. These will create a zero on the amplitude plot at around 1 kHz (for aluminum capacitors, somewhat higher for tantalum). The position of this zero depends solely on the tan δ (dissipation factor).

This changes the picture somewhat. Zero at fz (again shown approximately for a realistic 4700 μF aluminum capacitor) causes the plot to cross 0 dB at 20 dB/decade and makes the loop stable again.

So, such a regulator is actually stable for a much wider range of realistic loads than is apparent at the first glance. Long connection cables will further improve the situation. However, low ESR solid-state tantalum capacitors can still cause problems. These can be solved by increasing the bandwidth or with more complicated compensation networks, but these are left as an exercise for the reader.

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