## Thyristor regulator AC model

08.04.2010 12:40

It turns out that having a thyristor voltage regulator in a feedback loop isn't as simple as it seems. Actually, it's quite hard to keep the regulation stable over a wide range of load conditions and prevent it from oscillating. At least my previous experiments proved somewhat hard to adapt to work reliably in a pre-regulator regime where the load current can go from 0 to 2 amperes.

The stability problem is usually attacked by studying the circuit from the perspective of various well-known loop stability criteria, like phase and gain margin. However, this circuit is as non-linear as they get. Therefore Bode diagrams and such are out of the question without some major simplifications. Here's how the output voltage (thick) looks like when the reference voltage (thin) swings around a preset DC value. Obviously, the output contains frequencies not found in the input, hence the claim that this is a non-linear circuit. The output looks like this because the output voltage

• can only increase once every 10 ms (1 over 100 Hz, two times the line frequency), when the thyristors can fire, and
• can only decrease due to load current discharging the capacitors.

This circuit behaves more like a switch-mode power supply than a linear circuit. Unfortunately, the usual state-space averaging technique doesn't work here.

However, it does seem possible to approximate the gain and phase diagrams for a single input frequency with a simple one-pole transmission function:

A(j\omega) = \frac{1}{1 + j\frac{\omega}{\omega_p}}
\omega_p = \frac{2 \cdot I_{out}}{U_{in} \cdot C}

Where C is the output capacitance, Iout output current and Uin the amplitude of the AC reference voltage component. Of course, this holds only for input frequencies significantly lower than the line frequency (say 10 Hz and lower).

This appears to be a good enough approximation to use in practice when applying phase and gain margin criteria. Of course, it only allows rough approximations (think nearest order-of-magnitude, not nearest third-decimal). But it does show how stability relates to current and capacitance. It also shows that the frequency of the pole depends on the amplitude, so a circuit that's otherwise stable may go into oscillation if it receives a large enough disturbance from its set point - something I've also seen in practice.

In conclusion, here's a couple of simulated gain and phase diagrams compared with the approximation given above. The dots are the result of a time-domain simulation of the circuit while the lines represent the transfer function of the model above.

As you can see, the simulated gain follow the model quite nicely. On the other hand the phase plot is a bit off the mark. However the error is usually on the side of safety, since the simulated phase shift is less than one predicted by the model.  Posted by | Categories: Analog

What software did you use for the plots? Looks like Mathematica.

Posted by shears

That's gnuplot actually.

Default configuration produces plots that are ugly as hell, but with some tweaking it's possible to produce pretty graphs like this.

Posted by Tomaž