Avian’s Blog

Last time I talked about how Galaksija generates a composite video signal. I explained how the vertical and horizontal sync impulses are generated and how they are mixed together with the video signal. In this part I'll describe the part of the circuit that is responsible for generating that last part of the composite signal - the part that is actually carrying information about the picture that is drawn to the TV screen.

If you remember from my last post the video input into the composite video generator is at logic levels. Logical 1 (+5V) on that line means a black pixel and logical 0 (0V) means a white pixel. These levels must change in sync with the pixel clock - a clock signal that determines the length of one pixel on the screen.

Let's have a look at the first schematic:

On the right there is an 8-bit shift register (74HC166) and on the left is the character generator ROM. The ROM data outputs (8) are connected to the parallel inputs of the register. Low ROM address inputs (7) are connected to the Z80 data bus. High address inputs (9) are connected to the latch (more about that later). The pixel clock (1) is connected to the shift register's clock input. The "Shift out" output of the register is connected to the composite video generator (10).

So for every clock cycle the register will shift its contents one position to the right. On the first pixel clock cycle, the highest bit in the register will be on the video line, on the second cycle the second highest and so on until the 8th clock cycle. After that the register will be empty and has to be reloaded through its parallel input (8). For this to happen the "Load scan line" input (5) must be at logical 0 (the "Load enable" register input is active-low). During this time the first positive transition of the pixel clock will shift-in fresh 8 bits (representing the next 8 pixels to be drawn on screen) from the character ROM.

The character ROM obviously contains 8 bit slices of characters that will be displayed on the screen. Lower 7 address inputs determine the character to be displayed (so a maximum of 128 different characters can be displayed) while the upper 4 address inputs determine the scan line (row of pixels) that will be displayed on the current line.

Let's go through this again. The following things must happen for this scheme to work properly:

• Before every row gets drawn on the display the software has to set the proper scan line number on the latch and so set the upper 4 address inputs of the character ROM.
• Every 8 pixel clock cycles there must be a character code present on the processor's data bus.
• In sync with the character code the "Load scan line" input must go low for one pixel clock cycle.
• All this must be synchronized with the horizontal and vertical sync pulses that are added to the signal by the composite video generator.

We'll have a look at how the software does its part and the synchronization issues in one of the next parts. For now let's only have a look how the "Load scan line" gets generated.

Two 3-input NOR gates here form a simple logic circuit computes the "Load scan line" (5) signal from three control signals from the Z80 processor: the MREQ signal (3) goes low whenever the processor wants to access memory, RFSH (4) signal goes low whenever there is a memory refresh cycle and (2) is the CPU clock which is pixel clock divided by 2.

During the time that the picture is drawn on the screen, the Z80 CPU only performs a type of machine cycle that is called M1. Each M1 machine cycle takes 4 CPU clock cycles which is equal to 8 pixel clock cycles. During this time both MREQ and RFSH signals go low at a certain time, meaning that the "Load scan line" can go high for exactly one positive transition of the pixel clock, allowing 8 new pixels to be loaded in the shift register.

Again, here is a time diagram of all signals in this part of the circuit:

If you are familiar with the Z80 CPU you can probably already guess know how the software part of this system works. Next time I'll explain this time diagram in more detail and tell why exactly the correct character code appears on the CPU bus during this machine cycle.

Update: Only 7 data bus lines are connected to the character ROM, not 8. So only 128 different characters are possible.