Undersampling with a microcontroller ADC

08.10.2013 16:05

Analog-to-digital converters on microcontrollers aren't usually meant for high-frequency signals. The most common use case is a temperature sensor or something slow moving like that where you don't need a really high sample rate. At best you might want to sample audio signals. VESNA for instance has an ARM STM32F103 microcontroller that does at most 1 Msample/s.

The digital bandwidth of this ADC is limited to 500 kHz, half of its sampling frequency as per Shannon sampling theorem. However the theorem also says that you can undersample a band limited signal that is centered around an arbitrarily high frequency. In practice of course, you are limited with the analog bandwidth of the signal path in front of the analog-to-digital conversion.

The analog bandwidth isn't specified anywhere in the datasheets (at least nowhere I could find it). So I attempted to measure it using a signal generator and a simple bias circuit in front of an analog input pin of the microcontroller.

Circuit used to measure ADC analog bandwidth.

VESNA core board with a coaxial cable attachment.

The ADC was set to the maximum settings possible.

f_{adc} = 14 \mathrm{MHz}
f_{s} = 1 \mathrm{MHz}
t_{s} = 1.5 \mathrm{cycles} = 0.11 \mathrm{\mu s}

Below is an amplitude Bode plot of the system I measured:

Gain versus frequency plot for ADC on STM32F103

This shows that the -3 dB frequency is surprisingly high, at around 42 MHz. This is not something I expected - I thought the roll-off would start not much beyond the Nyquist frequency. Also, the specified sampling time of 0.11 μs gave me the impression that the analog bandwidth would be below 10 MHz. Actually, above 10 MHz the attenuation I saw might as well come from stray capacitances in the circuit and not from the converter itself.

Also interesting is the slight dip in amplitude between fs and 2fs. I'm not sure what is happening there. It is reproducible over two different microcontrollers.

If these measurements are correct this makes for interesting possibilities of using the ADC on VESNA for sampling band-limited high-frequency signals.

Posted by Tomaž | Categories: Analog

Comments

A signal at k times fs sampled with fs appears as a DC signal. So with the right amount of bad luck you can end up with any DC value between -A and A where A is the amplitude of the input signal. Your frequency is probably not exactly k fs so the signal ADC "sees" is a very low frequency signal which again can be misinterpreted as a signal with amplitude smaller than A. At least that's my guess.

Posted by AB

That is true, but if you look at the graph, the dip in the amplitude is approximately constant the whole way between fs and 2fs, not just near the integer multiples of fs. This means that the sampled signal went from DC to fs/2 and back to DC in that range.

Posted by Tomaž

IC manufactures today can hardly make transistors slower than 50 MHz so I am not surprised with your nice ADC range. Beware of DC zero beats at fs harmonics with clean sinus test input.

See Figure 37 on the STM32F103's datasheet. There's an RC filter acting as a sample-and-hold circuit. Table 45 indicates maximum values of R = 1 kΩ and C = 8 pF which works out to a cutoff frequency of about 20 MHz. Since these are max values, it makes sense that you'd find a slightly higher 3dB frequency, as you did.

Still, thanks for verifying this experimentally.

Posted by Décio

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