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In previous parts, I explained how synchronization impulses are generated and how they get mixed with the video signal from the character generator. I also described how character generator works and told a little bit about what must happen on the CPU bus in order for characters to be drawn on the screen. I also mentioned that everything must be timed perfectly in order for this scheme to work: software must be exactly synchronized with the hardware. As I promised this time I'll go into some detail about how this is achieved.

Synchronization of software execution with asynchronous events is usually done with hardware interrupts. This is a mechanism built into most of the CPUs that enables the designer to run a specific part of the program whenever some signal line becomes active. This mechanism is accurate enough for most purposes, but it is not perfect. For example, the CPU must finish computing the last instruction before it can begin executing the interrupt routine. This means that in the best possible scenario the interrupt timing is only accurate to the order of magnitude of the duration of a single instruction.

If you look carefully at the timing requirements for Galaksija's video circuitry you can see that this is not nearly accurate enough. The timing must be accurate to within one pixel clock period (around 160ns) while the longest Z80 instruction takes 23 CPU clock cycles (which is around 7500ns or 46 pixel clock periods)

Fortunately, the Z80 CPU provides a mechanism that can be used to correct the accuracy of interrupts. But before we go into that, let's first see where the interrupt impulses come from.

This is part of the clock generation circuit. Among other things it generates the video interrupt signal and horizontal and vertical sync clocks:

As you can see, the interrupt line (2) goes high 4ms after the vertical video sync (3). This signals the processor that it should start the interrupt routine and start putting video data on the CPU bus. Why 4ms after the vertical sync? This delay accounts for unused blank lines in the PAL standard that are above the visible area of the television screen.

Now you can see why there is special synchronization circuitry required. Without it the time CPU would start drawing the screen would depend on the interrupt delay, which is not deterministic and the picture would be blurred by those 46 pixels I mentioned before.

To provide better synchronization the following circuit is used:

Here we see the interrupt line (2) coming from the clock generator. U19, U20 and U21 halt the execution of the CPU until a video interrupt sync (5) goes low. If you remember from one of the previous parts, the interrupt sync line comes from the video generator and is basically an inverted horizontal sync impulse.

Let's have a look at signal waveforms at the moment the video interrupt occurs:

When the interrupt occurs, the CPU is executing an unknown instruction. It continues to do so for an unknown number of clock cycles. After its completion it enters an interrupt acknowledge cycle. This is a special version of the M1 machine cycle that produces a specific waveform on the M1 (6) and IOREQ (7) lines. This waveform is detected with a simple logic circuit (U20 and U19) and triggers a flip-flop U21. This puts logical 0 on the WAIT input (8) of the CPU.

Z80 CPU samples the WAIT input in most machine cycles at the falling edge of the CPU clock. If it detects a logical 0, it will halt the execution and insert dummy machine cycles known as wait states until the WAIT line is released.

This is done by the video interrupt sync signal (5) that resets U21 at the exactly the same moment as the first horizontal video impulse after the video interrupt. This causes the CPU to start executing the video interrupt routine in sync with the beginning of the first line to be drawn.

If you look at the previous waveform diagram you can see that there is one half of the horizontal sync period between the video interrupt (2) and the first horizontal sync impulse (that is also the video interrupt sync impulse (5)). Which means that there is plenty of time (approximately 30ms) available for the CPU to finish executing the last instruction and do the interrupt acknowledge cycle.

The mechanism described gives the software in the CPU a very accurate reference point from which all other timing required for the video signal generation can be derived. As you probably guessed the software that does that and actually takes care of feeding the character generator with data is again quite complicated. So the next part of this series of articles will be a bit less about electronics and a bit more about the software that drives it.